A liquid crystal display device (LCD), featured by thin thickness, light weight and low power consumption, has recently come into widespread use, and is being predominantly used as a display unit of a mobile equipment, such as a portable telephone set (mobile phones or cellular phones), a PDA (Personal Digital Assistant), a multi-function portable information terminal or a notebook PC. In these days, the technique for enlarging the display size or for coping with a moving picture has made progress such that it is possible nowadays to implement not only a mobile equipment but also a stationary large screen display device or a large display size liquid crystal TV. For such liquid crystal display device, a liquid crystal display device of the active matrix driving system is in use. As a display device of a thin thickness, a display device of the active matrix driving system employing an organic light emitting diode (OLED) has also been developed.
Referring to FIGS. 16A-16C, a typical configuration of a thin type display device of the active matrix driving system (a liquid crystal display device as well as an organic light emitting diode display device) will be briefly described. FIG. 16A is a block diagram showing essential portions of a thin type display device, and FIG. 16B is a diagram showing essential portions of a unit pixel of a display panel of a liquid crystal display device. FIG. 16C is a diagram showing essential portions of a unit pixel of a display panel of an organic light emitting diode display device. It is noted that, in FIGS. 16B and 16C, unit pixels are schematically shown as equivalent circuits.
Referring to FIG. 16A, the thin type display device of the active matrix driving system includes, as its typical components, a power supply circuit 940, a display controller 950, a display panel 960, a gate driver 970 and a data driver 980. The display device panel 960 includes unit pixels, each of which includes a pixel switch 964 and a display element 963 and which are arranged in a matrix array. In a color SXGA (Super eXtended Graphics Array) panel, for example, the matrix array is made up by 1280×3 pixel columns by 1024 pixel rows. On the display device panel 960, scan lines 961 that transmit scan signals output from the gate driver 970 to the respective unit pixels and data lines 962 that transmit gray scale voltage signals output from the data driver 980 are provided in a lattice-shaped configuration. The gate driver 970 and the data driver 980 are supplied with a clock signal CLK and a control signal under control by the display device controller 950. Image data are supplied to the data driver 980. Nowadays, image data are predominantly digital data. A power supply circuit 940 supplies the necessary power supply voltages to the gate driver 970 and to the data driver 980. The display device panel 960 includes a semiconductor substrate. As the display device panel 960 of a large screen display device, a semiconductor substrate formed by an insulating substrate, having thin film transistors (pixel switches) formed thereon, is widely used.
If, in the display device of FIG. 16A, the on/off of the pixel switch 964 is controlled by a scan signal. When the pixel switch 964 is turned on (made electrically conductive), the gray scale voltage signal, corresponding to the pixel data, is supplied to the display element 963. The display element 963 then is changed in luminance in response to the gray scale voltage signal, thus displaying an image. Each picture image equivalent data is updated for each frame period which is usually ca. 0.017 sec for 60 Hz driving. Each scan line 961 sequentially selects a pixel row (line) to turn on the pixel switch 964. During the time the pixel row is selected, the gray scale voltage signal is supplied from the data line 962 via the pixel switch 964 to the display element 963. There is also such an arrangement in which a plurality of pixel rows are simultaneously selected by the scan lines or driving is made by the frame frequency higher than 60 Hz.
Referring to FIGS. 16A and 16B, a liquid crystal display device has a display panel 960 including a semiconductor substrate and an opposite substrate. The semiconductor substrate has a matrix array of the pixel switches 964, as unit pixels, and transparent electrodes 973. The opposite substrate has a single transparent electrode 974 extending on its entire surface. These substrates are mounted facing each other with a gap in-between in which to charge a liquid crystal material. The display element 963, forming a unit pixel, includes the pixel electrode 973, the opposite substrate electrode 974, a liquid crystal capacitance 971 and an auxiliary capacitance 972. A backlight is provided as a light source on a back side of the display device panel.
When the pixel switch 964 is turned on by a scan signal from the scan lines 961, the gray scale voltage signal from the data line 962 is applied to the pixel electrode 973. The transmittance of the backlight, transferred through the liquid crystal, is changed due to the potential difference between each pixel electrode 973 and the opposite substrate electrode 974. The potential difference is kept for certain time duration by the liquid crystal capacitance 971 and the auxiliary capacitance 972 even after the pixel witch 964 is turned off, thus providing for display. It is noted that, in driving the liquid crystal display device, the voltage polarity is reversed between plus and minus polarities, with respect to the common voltage of the opposite substrate electrode 974, usually every frame period (inverted driving), in order to prevent deterioration of the liquid crystal. As typical of the driving of the data line is dot inversion driving where voltage polarities differ between neighboring pixels and column inversion driving where voltage polarities differ between neighboring data lines. In the dot inversion driving, gray scale voltage signals of the polarities different from one selection period (one data period) to another are output to the data line 962. In the column inversion driving, gray scale voltage signals of the polarities which are the same from one selection period (one data period) to another are output to the data line 962 in a frame period.
Turning to the organic light emitting diode display device, shown in FIGS. 16A and 16C, the display device panel 960 includes a semiconductor substrate carrying thereon a matrix array of larger numbers of unit pixels. Each of these unit pixels is composed of a pixel switch 964, an organic light emitting diode 982 and a thin film transistor (TFT) 981. The organic light emitting diode is formed by an organic film sandwiched between two thin film electrode layers. The TFT controls the current supplied to the organic light emitting diode 982. The organic light emitting diode 982 and the TFT 981 are connected in series with each other between power supply terminals 984, 985 supplied with different power supply voltages. An auxiliary capacitance 983 holds a control terminal voltage of the TFT 981. Meanwhile, the display element 963, correlated with a pixel, includes the TFT 981, organic light emitting diode 982, power supply terminals 984, 985 and the auxiliary capacitance 983.
When the pixel switch 964 is turned on (made electrically conductive) by the scan signal from the scan line 961, the gray scale voltage signal from the data line 962 is applied to the control terminal of the TFT 981. This causes light to be emitted from the organic light emitting diode 982 with the luminance corresponding to the current to make necessary display. Light emission is sustained even after the pixel switch 964 is turned off (made electrically non-conductive) since the gray scale voltage signal applied to the control terminal of the TFT 981 is kept for a certain time period by the auxiliary capacitance 983. In FIGS. 16A-16C, the pixel switch 964 and the TFT 981 implemented as Nch transistors are shown as an example. The pixel switch 964 and TFT 981 may, however, be implemented as Pch transistors. An organic EL element may also be connected to the side the power supply terminal 984. In the driving of the organic light emitting diode display device, no inverted driving, such as is used in the liquid crystal display device, need be used, such that a gray scale voltage signal for the pixel being displayed is output for one selection period (one data period).
Apart from the configuration of the organic light emitting diode display device in which display is made in keeping with the gray scale voltage signal from the data line 962, there is such a configuration in which the display device receives the gray scale current signal output from the data driver in order to make display. However, the following explanation of the present invention will be made only with reference to the configuration in which the display is in response to the gray scale voltage output from the data driver.
In FIG. 16A, it is only sufficient that the gate driver 970 provides at least bi-valued scan signals. On the other hand, the data driver 980 has to drive each data line 962 with multi-level gray scale voltage signals corresponding to the number of gray scales. For this reason, the data driver 980 includes a decoder for converting image data into gray scale voltage signals and a digital-to-analog converter (DAC) for amplifying the gray scale voltage signal to output the so amplified signal to the data line 962.
In mobile equipment, notebook PCs, monitors and television for high-end use, having a display of thin thickness configuration, such as liquid crystal display or organic light emitting diode display, the tendency is towards higher picture quality and larger numbers of colors that may be displayed. There is also a demand for larger numbers of hits for digital image data. The area of the multi-bit DAC depends upon the decoder configuration.
In a liquid crystal display, there is a demand for lowering of a driving power supply voltage of the liquid crystal. On the other hand, in the organic light emitting diode display, unlike the liquid crystal display, there is no necessity for polarity inversion. Also, the dynamic range (driving voltage range) with respect to the power supply voltage is broad. In light of the above, a CMOS switch is needed as a switch for a decoder of the digital-to-analog converter circuit in a data driver 980 for both the liquid crystal display and the organic light emitting diode display. The CMOS switch is comprised of a Pch transistor switch (Pch-SW) and an Nch transistor switch (Nch-SW) combined together. More specifically, the Pch switch and the Nch switch are connected in parallel to each other so that the directions of currents flowing in the drain-to-source paths of the switches will be the same, and complementary control signals are supplied to the gates of the switches which are controlled to be turned on and off in common.
However, if the Pch or Nch switches are all configured as CMOS switches, the decoder area is increased to raise the cost of the data driver.
In Patent Document 1 (JP Patent Kokai Publication No. JP-P2009-104056A), Patent Document 2 (JP Patent Kokai Publication No. JP-P2009-284310A) and in Patent Document 3 (JP Patent Kokai Publication No. JP-P2009-213132A), there are shown digital-to-analog converters as techniques relevant to the present invention. In these digital-to-analog converters, the number of reference voltages, selected by the decoder, is suppressed from increasing in order to suppress the number of bits of the input digital signal of the data driver from increasing to prevent that the number of elements that make up the decoder is increased.
FIG. 17 shows essential components of a digital-to-analog converter circuit disclosed in the Patent Documents 1 to 3 in common. The digital-to-analog converter circuit includes a decoder correlated with one of the positive and negative polarities of the LCD. The drawing has been drafted by the present inventor to illustrate the related techniques.
Referring to FIG. 17, the digital-to-analog converter of the Patent Documents 1 to 3 includes a reference voltage ensemble 820, a decoder 810 made up of first to (zS+1)th sub-decoders 811-1 to 811-(zS+1) and a sub-decoder 813, and an interpolation amplifier 830. The reference voltage ensemble 820 is an ensemble of reference voltages output from a reference voltage generator, not shown. The first to (zS+1)th sub-decoders input upper (m−n) bits out of m bits of m-bit digital data, and the sub-decoder 813 inputs lower n bits of the digital data. It is noted that S denotes integers representing powers of 2, inclusive of 1, namely 1, 2, 4, . . . , z denotes integers representing powers of 2, inclusive of 1, added to with 1, namely 2, 3, 5, 9, . . . , m denotes a preset positive integer not less than 3 and n denotes a preset positive integer not less than 2. In the digital-to-analog converter of FIG. 17, the number of the reference voltages, supplied to the decoder 810, is small as compared to the number of output levels supplied by the interpolation amplifier 830. In addition, the number of the transistor switches that make up the decoder is reduced. The decoder 810 is made up of transistor switches of a single conductivity type.
The reference voltage ensemble 820 includes a number of different reference voltages, in which voltage values are arrayed in accordance with an ordinal number sequence. These voltage values are grouped in (zS+1) reference voltage groups (820-1 to 820-(zS+1)). In the description to follow, multiplication mark (×) in the multiplication of symbols and numerical figures or that of symbols and other symbols are omitted for simplicity in notation. For example, zS denotes z×S, 2zS denotes 2×z×S and (j−1)zS denotes (j−1)×z×S.
The first reference voltage set 820-1 has {(j−1)zS+1}th reference voltages (Vr{(j−1)zS+1}), where j may assume values 1, 2, . . . , and h, where h being a positive integer not less than 2. In case the index number j assumes the total of the integer values of 1 to h, the reference voltage set 820-1 has the reference voltage Vr{1}, Vr{zS+1}, Vr{2zS+1}, . . . , and Vr{(h−1)zS+1}, at intervals of (zS) reference voltages.
The second reference voltage set 820-2 has {(j−1)zS+2}nd reference voltages (Vr{(j−1)zS+2}). In case the index number j assumes the total of the integer values of 1 to h, the reference voltage set 820-2 has the reference voltage Vr{2}, Vr{zS+2}, Vr{2zS+2}, . . . , and Vr{(h−1)zS+2}, at intervals of (zS) reference voltages.
In similar manner, the (zS+1)th reference voltage set 820-(zS+1) has {(j−1)zS+(zS+1)}th, that is, ((jzS+1)th, reference voltages (Vr{(j−1)zS+(zS+1)})=Vr(jzS+1). In case the index number j assumes the total of the integer values of 1 to h, the (zS+1)th reference voltage set 820-(zS+1) has the reference voltage Vr{(zS+1)}, Vr{2zS+1}, Vr{3zS+1}, . . . , and Vr{hzS+1}, at intervals of (zS) reference voltages.
In case the index number j assumes the total of integer values of 1 to h, the reference voltage ensemble 820 has (hzS+1) different reference voltages. There are cases where there partially lack the index numbers j in association with the case where there partially lack reference voltages.
Each of the first to (zS+1)th sub-decoders 811-1 to 811-(zS+1) is able to select each one reference voltage from each of the reference voltage groups (820-1 to 820-(zS+1)), depending upon the value of the (m−n) bits (D(m−1) to Dn and D(m−1)B to DnB) of the m-bit digital signal. It is noted that D(m−1)B to DnB are complementary signals of D(m−1) to Dn, respectively. It is also noted that the bit signals (D0, D0B) are LSBs (Least Significant Bits) and the bit signals (D(m−1) and D(m−1)B) are MSBs (Most Significant Bits), with the sides of the smaller and larger values of the symbol m being the lower side bits and upper side bits, respectively.
The sub-decoder 813 selects first and second voltages Vo1 and Vo2 from (zS+1) or less reference voltages, which have been selected by the first to (zS+1)th sub-decoders 811-1 to 811-(zS+1), depending upon the values of the lower side n bits (D(n−1) to D0 and (D(n−1)B to D0B) of the m-bit digital signal.
The interpolation amplifier 830 receives the first and second voltages Vo1 and Vo2, selected by the sub-decoder 813, at P inputs, inclusive of duplications, as V(T1), V(T2), . . . , and V(TP), to output voltage levels resulting from weighted averaging of the voltages V(T1), V(T2), . . . , and V(TP) at a preset ratio. That is, the interpolation amplifier 830 is able to generate a plurality of voltage levels by interpolation of two voltages (Vo1, Vo2), which may be the same or different, and which have been selected by the decoder 810.
The reference voltages of the reference voltage ensemble 820 from Vr1 to Vr(hzS+1) are at respective different voltage levels. That is, VrX, where X=1 to (hzS+1), are arrayed in an ordinal sequence so as to increase or decrease monotonically in connection with the ascending or descending order of the value X.
More specifically, the interpolation amplifier 830 may be so configured that, with P=2, its two inputs T1 and T2 receive two voltages (Vo1, Vo2), with the voltages V(T1) and V(T2), supplied to the two inputs T1 and T2, being interpolated at 1:1 to yield (Vout={V(T1)+V(T2)}/2), as disclosed in Patent Documents 1 to 3. It may also be so configured that, with P=3, its three inputs T1, T2 and T3 receive two voltages (Vo1, Vo2), with the voltages V(T1), V(T2) and V(T3), supplied to the three inputs T1, T2 and T3, being weight-averaged at a ratio of 1:1:2 to produce Vout (V(T1)+V(T2)+2×V(T3))/4, as disclosed in Patent Documents 1 and 2.
The first to (zS+1)th sub-decoders 811-1 to 811-(zS+1) receive upper side (m−n) bit (D(m−1) to Dn and D(m−1)B to DnB in common. The (zS+1) or less reference voltages, as selected by the sub-decoders 811-1 to 811-(zS+1), are reference voltages in the reference voltage ensemble 820 differing in voltage levels and contiguous in ordinal voltage values.
For example, if the reference voltage Vr{(j−1) zS+1} has been selected in the first sub-decoder 811-1, the reference voltage Vr{(j−1) zS+2}, reference voltage Vr{(j−1) zS+3}, . . . , the reference voltage Vr(jzS+1) are selected in the second sub-decoder, third sub-decoder, . . . , and the (zS+1)th sub-decoder, respectively.
The following describes the grouping in the reference voltage ensemble 820 and the reference voltages selected by the sub-decoders 811-1 to 811-(zS+1) of FIG. 17.
FIG. 18 schematically shows an example grouping of the reference voltage ensemble 820 of FIG. 17, and has been drafted by the present inventor for illustrating the related technique. Referring to FIG. 18, a plurality of reference voltages, (hzS+1) reference voltages at the maximum, of the reference voltage ensemble 820 of FIG. 17, may be represented by a two-dimensional array of (zS+1) rows and h columns. In this two-dimensional array, the first to (zS+1)th reference voltage groups (820-1 to 820-(zS+1)) are allocated to rows, and the ordinal sequence numbers, such as 1, 2, . . . , h−1 and h, where h in the reference voltage groups of the reference voltages belonging to the particular groups, are allocated to columns. It is noted that the two-dimensional array of FIG. 18 is not present in reality, for example, such as in the decoder 810, but is a kind of representation format suited for explaining the grouping/ordinal sequence of the reference voltages.
The element of the row i column j, allocated to the two-dimensional array, where i is an integer not less than 1 and not greater than (zS+1), j is an integer not less than 1 and not greater than h and h is an integer not less than 2, corresponds to the reference voltage Vr((j−1)zs+i).
That is, the first reference voltage set 820-1 is composed of (Vr1, Vr(zS+1), Vr(2zS+1), . . . , and Vr{(h−1)(zS+1)}, allocated to the first row of the two-dimensional array, with the voltage values spaced apart from one another by zS reference voltages.
The second reference voltage set 820-2 is composed of (Vr2, Vr(zS+2), Vr(2zS+2), . . . , and Vr{(h−1)(zS)+2}, allocated to the second row of the two-dimensional array, with the voltage values being spaced apart from one another by zS reference voltages.
The i-th reference voltage set 820-i is composed of (Vr(i), Vr(zS+i), Vr(2zS+i), . . . , and Vr{(h−1)(zS)+i}, allocated to the i-th row of the two-dimensional array, with the voltage values being spaced apart from one another by zS reference voltages.
The (zS+1)th reference voltage set 820-(zS+1) is composed of (Vr(zS+1), Vr(2zS+1), Vr(3zS+1), . . . , and Vr{hzS+1}), allocated to the (zS+1)th row of the two-dimensional array, with the voltage values being spaced apart from one another by zS reference voltages.
The first to (h−1)th reference voltage in the (zS−1)th reference voltage set 820-(zS+1) (the reference voltages allocated to the first to the (h−1)th columns of the (zS+1)th row of the two-dimensional array) are the same as the second to the h-th reference voltages in the reference voltage set 820-1 (reference voltages allocated to the second to the h-th columns of the first row of the two-dimensional array).
The columns of the two-dimensional array of FIG. 18 are in keeping with the upper order (m−n) bits (D(m−1) to Dn and D(m−1)B to DnB) of the m-bit digital signal of FIG. 17. The reference voltages selected by the first to (zS+1)th sub-decoders 811-1 to 811-(zS+1) are reference voltages allocated to any one of the first to hth columns of FIG. 18 corresponding to the upper side (m−n) bits.
It is noted that FIG. 18 shows the location relationship among respective different (hzS+1) reference voltages of from Vr1 to Vr(hzS+1). In these reference voltages, any suitable preset number of the reference voltages as from Vr1 may be lacking. Also, any suitable preset number of the reference voltages as from a voltage ahead of the voltage Vr(hzS+1) down to the voltage Vr(hzS+1) may be lacking.
The relationship between FIG. 17 and the digital-to-analog converter shown in Patent Documents 1 to 3 will now be described.
(a) In the case of S=1 and z=2(zS+1=3), the digital-to-analog converter of FIG. 17 includes first to third sub-decoders supplied with a plurality of reference voltages grouped into three reference voltage groups and with upper side (m−n) bits of the m-bit digital signal. The digital-to-analog converter also includes a sub-decoder supplied with outputs of the first to third sub-decoders and with lower n bits of the m-bit digital signal to select first and second voltages (Vo1, Vo2). The digital-to-analog converter further includes an interpolation amplifier supplied with the first and second voltages (Vo1, Vo2) at its P inputs to weight-average the voltages received at a preset weight ratio to output a resulting voltage. Such case corresponds to FIG. 1 of Patent Document 1. It is noted that the symbol k of Patent Document 1 (FIG. 1) corresponds to a symbol j in FIG. 17.(b) In the case of S=2, z=2(zS+1=5), and P=2, the digital-to-analog converter of FIG. 17 includes first to fifth sub-decoders supplied with a plurality of reference voltages grouped into five reference voltage groups and with upper side (m−n) bits of the m-bit digital signal. The digital-to-analog converter also includes a sub-decoder supplied with outputs of the first to fifth sub-decoders and with lower n bits of the m-bit digital signal to select first and second voltages (Vo1, Vo2). The digital-to-analog converter further includes an interpolation amplifier supplied with the first and second voltages (Vo1, Vo2) at its two inputs to average (interpolate) the voltages received at a preset ratio to output a resulting voltage. Such case corresponds to FIG. 3 of Patent Document 2. It is noted that the symbol S of Patent Document 2 corresponds to a symbol (zS) in FIG. 17.(c) In the case of S=4, z=2 (zS+1=9), and P=2, the digital-to-analog converter of FIG. 17 includes first to ninth sub-decoders supplied with a plurality of reference voltages grouped into nine reference voltage groups and with upper side (m−n) bits of the m-bit digital signal. The digital-to-analog converter also includes a sub-decoder supplied with outputs of the first to ninth sub-decoders and with lower n bits of the m-bit digital signal to select first and second voltages (Vo1, Vo2). The digital-to-analog converter further includes an interpolation amplifier supplied with the first and second voltages (Vo1, Vo2) at its two inputs to average (interpolate) the voltages received at a preset ratio to output a resulting voltage. Such case corresponds to FIG. 9 of Patent Document 2.(d) In the case of S=2, z=2 (zS+1 and P=3, the digital-to-analog converter of FIG. 17 includes first to fifth sub-decoders supplied with a plurality of reference voltages grouped into five reference voltage groups and with upper side (m−n) bits of the m-bit digital signal. The digital-to-analog converter also includes a sub-decoder supplied with outputs of the first to fifth sub-decoders and with lower n bits of the m-bit digital signal to select first and second voltages (Vo1, Vo2). The digital-to-analog converter further includes an interpolation amplifier supplied with the first and second voltages (Vo1, Vo2) at its three inputs to weight-average the voltages received at a ratio of 1:1:2 to output a resulting voltage. Such case corresponds to FIG. 16 of Patent Document 2.(e) In the case of S being an integer equal to powers of 2, inclusive of 1, and being not less than 2, z=3 (zS+1=3S+1), and P=2, the digital-to-analog converter of FIG. 17 includes first to (3S+1)th sub-decoders supplied with a plurality of reference voltages grouped into (3S+1) reference voltage groups and with upper side (m−n) bits of the m-bit digital signal. The digital-to-analog converter also includes a sub-decoder supplied with outputs of the first to (3S+1)th sub-decoders and with lower n bits of the m-bit digital signal to select first and second voltages (Vo1, Vo2). The digital-to-analog converter further includes an interpolation amplifier supplied with the first and second voltages (Vo1, Vo2) at its two inputs to average (interpolate) the voltages received at a ratio of 1:1 to output a resulting voltage. Such case corresponds to FIG. 1 of Patent Document 3.(f) In the case of S=2, z=3 (zS+1=7), and P=2, the digital-to-analog converter of FIG. 17 includes first to seventh sub-decoders supplied with a plurality of reference voltages grouped into seven reference voltage groups and with upper side (m−n) bits of the m-bit digital signal. The digital-to-analog converter also includes a sub-decoder supplied with outputs of the first to seventh sub-decoders and with lower n bits of the m-bit digital signal to select first and second voltages (Vo1, Vo2). The digital-to-analog converter further includes an interpolation amplifier supplied with the first and second voltages (Vo1, Vo2) at its two inputs to average (interpolate) the voltages received at a ratio of 1:1 to output a resulting voltage. Such case corresponds to FIG. 3 of Patent Document 3.(g) In the case of S=1, z=3 (zS+1=4), and P=2, the digital-to-analog converter of FIG. 17 includes first to fourth sub-decoders supplied with a plurality of reference voltages grouped into four reference voltage groups and with upper side (m−n) bits of the m-bit digital signal. The digital-to-analog converter also includes a sub-decoder supplied with outputs of the first to fourth sub-decoders and with lower n bits of the m-bit digital signal to select first and second voltages (Vo1, Vo2). The digital-to-analog converter further includes an interpolation amplifier supplied with the first and second voltages (Vo1, Vo2) at its two inputs to average (interpolate) the voltages received at a ratio of 1:1 to output a resulting voltage. Such case corresponds to FIG. 7 of Patent Document 3.
As may be seen from above, various arrangements based upon various combinations of the symbols S, z and P in FIG. 17 correspond to the arrangements of the digital-to-analog converter disclosed in Patent Documents 1 to 3. The symbol S is an integer representing powers of 2, inclusive of 1, namely 1, 2, 4, . . . , the symbol z is an integer representing powers of 2, inclusive of 1, added to with 1, namely 2, 3, 5, 9, . . . . The symbol P is 2 or 3. It is noted that the results of analysis by the present inventor have revealed that a digital-to-analog converter of the configuration other than that disclosed in the Patent Documents 1 to 3 may similarly be implemented by various combinations of particular values of the above mentioned symbols. As for the relationship between the multiple reference voltages and the voltage level that may be output from the interpolation amplifier, reference may be made to data disclosed in the Patent Documents 1 to 3.
The following describes the configuration of the sub-decoders 811-1 to 811-(zS+1) of FIG. 17. FIG. 19 shows the configuration of an i-th sub-decoder 811-i (i=1 to (zS+1)), and has been drafted by the present inventor in order to illustrate the related technique. It is assumed that the reference voltage ensemble 820 has (hzS+1) respective different reference voltages from Vr1 to Vr(zS+1). In this case, the first to the (zS+1)th sub-decoders are of the same circuit configuration, with the difference being in the sets of the reference voltages supplied to the sub-decoders. In FIG. 19, the leftmost reference voltage set 820-1 is supplied to the first sub-decoder 811-1, the reference voltage set 820-2 is supplied to the second sub-decoder 811-2 and the reference voltage set 820-(zS+1) is supplied to the (zS+1)th sub-decoder 811-(zS+1). However, the sub-decoder shown is only the i-th sub-decoder. In FIG. 19, the first to the (zS+1)th sub-decoders 811-i, where i is 1 to (zS+1), select reference voltages Vr{(j−1)zS+1}, Vr{(j−1)zS+2}, . . . , Vr{(jzS+1}, bearing the ordinal sequence number of j in the respective reference voltage groups (820-1 to 820-(zS+1)), depending upon the values of upper side (m−n) bits of the m-bit digital signal (D(m−1) to Dn and D(m−1)B to DnB). These reference voltages, bearing the ordinal sequence number of j, correspond to the elements of the column j (j-th column) of the two-dimensional array of FIG. 18.
In FIG. 19, the sub-decoder 811-i, where i=1 to (zS+1), inputs h reference voltages and sequentially makes selection on the basis of (m−n) bits (D(m−1) to Dn and D(m−1)B to DnB) of the m-bit digital signal in a sequence of from lower side bits (Dn, DnB) to the upper side bits. The sub-decoder 811-i is thus a tournament configuration switch, and selects a sole voltage with D(m−1), D(m−1)B to output the so selected voltage.
Each switch is composed by a pass transistor of a single conductivity type. In case the switch is composed by an Nch transistor, Dn to D(m−1) are supplied to bit signal lines b1 to b5, whilst DnB to D(m−1)B are supplied to bit signal lines b1b to b5b. In case the switch is composed by a Pch transistor, DnB to D(m−1)B are supplied to the hit signal lines b1 to b5, whilst Dn to D(m−1) are supplied to the bit signal lines b1b to b5b. FIG. 19 shows, for explanation sake, the configuration of a sub-decoder of a 5-bit tournament configuration made up of a number of Nch transistors.
The following describes the configuration of the sub-decoder 813 of FIG. 17. The sub-decoder 813 differs in configuration depending upon the values of the symbols A, z and P and upon the conductivity types of the transistor switches. In the following, a typical example of an Nch transistor configuration will be explained.
FIG. 20 shows a configuration of a sub-decoder 813-A, where S=2, z=2 (zS+1=5) and P=2. As for details, see Patent Document 2. The Nch transistor switches, connected to (D2B, D2), select one out of (Vr(4j−3), Vr(4j−1)), one out of (Vr(4j−2), Vr(4j)) and one out of (Vr(4j−1), Vr(4j+1)), respectively, to output the selected three voltages at nodes n3, n4 and n5. In case D2=1 (HIGH), (n3, n4, n5)=(Vr(4j−1), Vr(4j), Vr(4j+1)), whereas, if D2B=1, (n3, n4, n5)=(Vr(4j−3), Vr(4j−2), Vr(4j)).
The Nch transistor switches, connected to (D1B, D1), select one out of (node n3, node n4) and one out of (node n4, node n5) to output the resulting two at nodes T1 and n2. If D1 is 1, (T1, n2)=(n4, n5) and, if D1B is 1, (T1, n2)=(n3, n4).
The Nch transistors, connected to (D0B, D0), select one out of the nodes T1 and n2 to output the resulting one at node T2. If D0 is 1, T2=n2 and, if D0B is 1, T2=T1.
The nodes T1 and T2 output two voltages having contiguous ordinal sequence numbers or, in duplication, a single voltage (two same voltages), as first and second voltages (Vo1, Vo2), to the interpolation amplifier 830. The voltages V(T1) and V(T2) at the respective nodes T1 and T2 are interpolated at a ratio of 1:1 and the resulting voltage is output to the interpolation amplifier 830.
FIG. 21 shows a configuration of a sub-decoder 813-B where S=2, z=2 (zS+1=5) and P=3. As for details, see Patent Document 2. The Nch transistor switches, connected to (D3B, D3), select one out of (Vr(4j−3), Vr(4j−1)), one out of (Vr(4j−2), Vr(4j) and one out of (Vr(4j−1), Vr(4j+1), respectively, to output the selected three voltages at nodes n13, n14 and n15. In case D3=1 (HIGH), (n13, n14, n15) (Vr(4j−1), Vr(4j), Vr(4j+1)), whereas, if D3B=1, (n13, n14, n15)=(Vr(4j−3), Vr(4j−2), Vr(4j)).
The Nch transistor switches, connected to (D2B, D2), select one out of (node n13, node n14) and one out of (node n14, node n15) to output the resulting two at nodes T2 and n12. If D2 is 1, (T2, n12)=(n14, n15) and, if D2B is 1, (T2, n12)=(n13, n14).
The Nch transistor switches, connected to (D1B, D1), select one of the nodes T2, n12 to output the selected one at the node T3. In case D1 is 1, T3=n12, whereas, in case D1B=1, and T3=T2.
The Nch transistor switches, connected to (D0B, D0), select one of the nodes T2, n12 to output the selected one at the node T1. In case D0 is 1, T1=n12, whereas, in case D0B=1, T1=T2.
The nodes T1, T2 and T3 output two voltages having contiguous ordinal sequence numbers, or a single voltage in duplication (two same voltages), as first and second voltages (Vo1, Vo2) to the interpolation amplifier 830. The interpolation amplifier 830 weight-averages (or interpolates) voltages V(T1), V(T2) and V(T3) of the respective nodes T1, T2 and T3 at a ratio of 1:1:2 to output a resulting weight averaged voltage.
FIG. 22 shows a configuration of a sub-decoder 813-C where S=1, z=3(zS+1=4) and P=2. As for details, see Patent Document 3. The Nch transistor switches, connected to (D0B, D0), select one out of (Vr(3j−2), Vr(3j−1)), one out of (Vr(3j−1), Vr(3j) and one out of (Vr(3j−1), Vr(3j−2), respectively, to output the selected three voltages at nodes n24, n25, n26 and n27. In case D0=1 (HIGH), (n24, n25, n26, n27)=(Vr(3j−1), Vr(3j), Vr(3j+1) Vr(3j−2), whereas, if D0B=1, (n24, n25, n26, n27)=(Vr(3j−2), Vr(3j−1), Vr(3j), Vr(3j−1)).
The Nch transistor switches, connected to (D1B, D1), select one out of (node n24, node n25), one out of (Vr(3j−2), node n27) and one out of (Vr(3j−1), Vr(3j)) to output the resulting three voltages at nodes 21, 22 and 23. If D1 is 1 (HIGH), (n21, n22, n23)=(n25, n27, Vr(3j)) and, if D1B is 1, (n21, n22, n23) (n24, Vr(3j−2), Vr(3j−1)).
The Nch transistor switches, connected to (D2B, D2), select one out of the nodes n21, n26 and one out of nodes n22, n23 to output the selected one at the nodes T1 and T2. In case D2 is 1 (HIGH), (T1, T2)=(n26, n23), whereas, in case D2B=1, (T1, T2)=(n21, n22).
The nodes T1 and T2 output either two voltages or a single voltage (two same voltages), in duplication, as first and second voltages (Vo1, Vo2), to the interpolation amplifier 830. This interpolation amplifier 830 weight averages (or interpolates) voltages V(T1) and V(T2) of the nodes T1 and T2 at a ratio of 1:1 to output a resulting averaged voltage.